EDF - OnePIC MCU
v1.1.0
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00001 00007 #ifndef __BSP_H 00008 #define __BSP_H 00009 #include <stdlib.h> 00010 #include <stdint.h> 00011 #include <stdio.h> 00012 #include "OnePIC_lcd.h" 00013 #include "OnePIC_pot.h" 00014 #include "OnePIC_switch.h" 00015 00016 #include "TimeDelay.h" 00017 00018 #define LED_ON 1 00019 #define LED_OFF 0 00020 00021 #include <p32xxxx.h> 00022 #include <plib.h> 00023 #include <sys/attribs.h> 00024 00025 // Clocks 00026 #define GetSystemClock() 20000000UL 00027 #define SYS_FREQ (20000000UL) 00028 #define GetPeripheralClock() (GetSystemClock()) 00029 #define GetInstructionClock() (GetSystemClock()) 00030 00031 // ADC channels available 00032 #define MAX_ADC_CHANNELS 16 00033 00034 // Key to ADC Channel assignment 00035 #define DIRECTKEY1_CHANNEL CHANNEL_AN0 00036 #define DIRECTKEY2_CHANNEL CHANNEL_AN1 00037 #define DIRECTKEY3_CHANNEL CHANNEL_AN2 00038 #define DIRECTKEY4_CHANNEL CHANNEL_AN3 00039 #define DIRECTKEY5_CHANNEL CHANNEL_AN4 00040 00041 // GPIO initialization values 00042 #define INIT_TRISB_VALUE 0x0000 00043 #define INIT_TRISC_VALUE 0x0000 00044 #define INIT_TRISD_VALUE 0x0000 00045 #define INIT_TRISE_VALUE 0x0000 00046 #define INIT_TRISF_VALUE 0x0000 00047 #define INIT_TRISG_VALUE 0x0000 00048 00049 #define INIT_PORTB_VALUE 0x0000 00050 #define INIT_PORTC_VALUE 0x0000 00051 #define INIT_PORTD_VALUE 0x0000 00052 #define INIT_PORTE_VALUE 0x0000 00053 #define INIT_PORTF_VALUE 0x0000 // Not used 00054 #define INIT_PORTG_VALUE 0x0000 00055 00056 /****************************************************************************** 00057 * ADC 00058 ******************************************************************************/ 00059 #define ADC_BUFFER 00060 #define ADC_OPERATING_MODE AD1CON1bits.ON 00061 #define ADC_STOP_IN_IDLE AD1CON1bits.SIDL 00062 #define ADC_DATA_OUTPUT_FORMAT AD1CON1bits.FORM 00063 #define ADC_CONV_SOURCE AD1CON1bits.SSRC 00064 #define ADC_AUTO_SAMPLE AD1CON1bits.ASAM 00065 #define ADC_SAMPLE_ENABLE AD1CON1bits.SAMP 00066 #define ADC_CONV_DONE AD1CON1bits.DONE 00067 00068 #define ADC_VOLTAGE_REF_CONFIG AD1CON2bits.VCFG 00069 #define ADC_MUX_A_CH_SEL AD1CON2bits.CSCNA 00070 #define ADC_BUFFER_FILL_STAT AD1CON2bits.BUFS 00071 #define ADC_SAMPLE_SEQ_INT_SEL AD1CON2bits.SMPI 00072 #define ADC_BUFFER_MODE_SEL AD1CON2bits.BUFM 00073 #define ADC_ALT_SAMPLE_MODE AD1CON2bits.ALTS 00074 00075 #define ADC_CONV_CLK_SRC AD1CON3bits.ADRC 00076 #define ADC_AUTO_SAMPLE_TIME AD1CON3bits.SAMC 00077 #define ADC_CONV_CLK_PERIOD_SEL AD1CON3bits.ADCS 00078 00079 00080 /****************************************************************************** 00081 * ADC 00082 * *****************************************************************************/ 00083 // 10/5/2011 10:25:22 AM: PIC32 ADC: 00084 /*** POT RB11 AN11 ***********************************************************/ 00085 #define ADC_POT_IO_BIT 11 00086 #define ADC_POT_IO_CH_BIT 11 00087 #define ADC_POT_LATCH LATB 00088 #define ADC_POT_TRIS TRISB 00089 /*** MIC RB8 AN8 ***********************************************************/ 00090 #define ADC_MIC_IO_BIT 8 00091 #define ADC_MIC_IO_CH_BIT 8 00092 #define ADC_POT_LATCH LATB 00093 #define ADC_POT_TRIS TRISB 00094 /*** UP RB4 AN4 ***********************************************************/ 00095 #define ADC_UP_IO_BIT 4 00096 #define ADC_UP_IO_CH_BIT 4 00097 #define ADC_POT_LATCH LATB 00098 #define ADC_POT_TRIS TRISB 00099 /*** DOWN RB1 AN1 ***********************************************************/ 00100 #define ADC_DOWN_IO_BIT 1 00101 #define ADC_DOWN_IO_CH_BIT 1 00102 #define ADC_POT_LATCH LATB 00103 #define ADC_POT_TRIS TRISB 00104 /*** LEFT RB0 AN0 ***********************************************************/ 00105 #define ADC_LEFT_IO_BIT 0 00106 #define ADC_LEFT_IO_CH_BIT 0 00107 #define ADC_POT_LATCH LATB 00108 #define ADC_POT_TRIS TRISB 00109 /*** RIGHT RB3 AN3 ***********************************************************/ 00110 #define ADC_RIGHT_IO_BIT 3 00111 #define ADC_RIGHT_IO_CH_BIT 3 00112 #define ADC_POT_LATCH LATB 00113 #define ADC_POT_TRIS TRISB 00114 /*** ENTER RB2 AN2 ***********************************************************/ 00115 #define ADC_ENTER_IO_BIT 2 00116 #define ADC_ENTER_IO_CH_BIT 2 00117 #define ADC_POT_LATCH LATB 00118 #define ADC_POT_TRIS TRISB 00119 00120 /****************************************************************************** 00121 * SPI 00122 ******************************************************************************/ 00123 #define SPI1_BUFFER 00124 #define SPI1_ENABLE SPI2CONbits.ON 00125 #define SPI1_STOP_IN_IDLE SPI2CONbits.SIDL 00126 // XXX 10/10/2011 3:13:33 PM: 24/32 have different buffer structers, use simplest non-enhanced mode 00127 #define SPI1_BUFFER_ELEMENT_CNT 00128 #define SPI1_SR_EMPTY SPI2STATbits.SRMT 00129 #define SPI1_RX_OVERFLOW SPI2STATbits.SPIROV 00130 #define SPI1_RX_FIFO_EMPTY SPI2STATbits.RXBUFELM 00131 #define SPI1_INT_MODE_SEL // XXX 10/10/2011 3:15:12 PM Different int selections, use Polled mode 00132 #define SPI1_TX_BUFFER_FULL SPI2STATbits.SPITBF 00133 #define SPI1_RX_BUFFER_FULL SPI2STATbits.SPIRBF 00134 00135 #define SPI1_SCK_DISABLE 00136 #define SPI1_SDO_DISABLE SPI2CONbits.DISSDO 00137 // XXX 10/10/2011 2:35:36 PM: PIC32x has 8/16/32 option, PIC24 has 8/16bit options, config not the same 00138 #define SPI1_MODE16_SEL 00139 #define SPI1_SAMPLE_PHASE SPI2CONbits.SMP 00140 #define SPI1_CLK_EDGE_SEL SPI2CONbits.CKE 00141 #define SPI1_SS_ENABLE SPI2CONbits.SSEN 00142 #define SPI1_CLK_POL_SEL SPI2CONbits.CKP 00143 #define SPI1_MASTER_ENABLE SPI2CONbits.MSTEN 00144 #define SPI1_SEC_PRESCALE 00145 #define SPI1_PRI_PRESCALE 00146 00147 #define SPI1_FRAMED_MODE_ENABLE SPI2CONbits.FRMEN 00148 #define SPI1_FRAME_SYNC_PULSE_DIR SPI2CONbits.FRMSYNC 00149 #define SPI1_FRAME_SYNC_PULSE_POL SPI2CONbits.FRMPOL 00150 #define SPI1_FRAME_SYNC_PULSE_EDGE SPI2CONbits.SPIFE 00151 #define SPI1_ENHANCE_BUFFER_ENABLE SPI2CONbits.ENHBUF 00152 00153 // NA on PIC24: 00154 // XXX 10/10/2011 2:41:02 PM: Master Mode Slave Select enable 00155 // XXX 10/10/2011 2:41:17 PM: FRame sync pulse width 00156 // XXX 10/10/2011 2:51:32 PM: FRZ 00157 // XXX 10/10/2011 2:57:34 PM: TX buffer interrupt mode sel 00158 // XXX 10/10/2011 2:57:49 PM: RX buffer int mode sel 00159 /********************************************************************** 00160 * LEDs 00161 **********************************************************************/ 00162 #define gpLED_8_TRIS TRISDbits.TRISD6 00163 #define gpLED_7_TRIS TRISDbits.TRISD5 00164 #define gpLED_6_TRIS TRISDbits.TRISD12 00165 #define gpLED_5_TRIS TRISDbits.TRISD11 00166 #define gpLED_4_TRIS TRISDbits.TRISD10 00167 #define gpLED_3_TRIS TRISDbits.TRISD9 00168 #define gpLED_2_TRIS TRISDbits.TRISD8 00169 #define gpLED_1_TRIS TRISDbits.TRISD7 00170 00171 #define gpLED_8 LATDbits.LATD6 00172 #define gpLED_7 LATDbits.LATD5 00173 #define gpLED_6 LATDbits.LATD12 00174 #define gpLED_5 LATDbits.LATD11 00175 #define gpLED_4 LATDbits.LATD10 00176 #define gpLED_3 LATDbits.LATD9 00177 #define gpLED_2 LATDbits.LATD8 00178 #define gpLED_1 LATDbits.LATD7 00179 00180 #define gpLED_UP_TRIS TRISCbits.TRISC1 00181 #define gpLED_DOWN_TRIS TRISCbits.TRISC4 00182 #define gpLED_RIGHT_TRIS TRISCbits.TRISC2 00183 #define gpLED_LEFT_TRIS TRISCbits.TRISC3 00184 00185 #define gpLED_UP LATCbits.LATC1 00186 #define gpLED_DOWN LATCbits.LATC4 00187 #define gpLED_RIGHT LATCbits.LATC2 00188 #define gpLED_LEFT LATCbits.LATC3 00189 00190 /********************************************************************** 00191 * Switch 00192 **********************************************************************/ 00193 #define SW1_TRIS gpLED_1_TRIS 00194 #define SW1_PORT PORTDbits.RD7 00195 #define SW1_LATCH LATDbits.LATD7 00196 /********************************************************************** 00197 * I2C 00198 **********************************************************************/ 00199 #define I2C_MODULE_ENABLE I2C1CONbits.ON 00200 #define I2C_DISABLE_SLEW_CONTROL I2C1CONbits.DISSLW 00201 #define I2C_INTERRUPT_FLAG IFS0bits.I2C1MIF 00202 #define I2C_INTERRUPT_ENABLE IEC0bits.I2C1MIE 00203 #define I2C_BRG I2C1BRG 00204 #define I2C_BCL_MASTER_BUS_COLLISION I2C1STATbits.BCL 00205 #define I2C_SEN_START_CONDITION_ENABLE I2C1CONbits.SEN 00206 #define I2C_TRANSMIT_REGISTER I2C1TRN 00207 #define I2C_RECIEVE_REGISTER I2C1RCV 00208 #define I2C_REPEATED_START_ENABLE I2C1CONbits.RSEN 00209 #define I2C_ACK_STATUS I2C1STATbits.ACKSTAT 00210 #define I2C_STOP_CONDITION_ENABLE I2C1CONbits.PEN 00211 #define I2C_RECIEVE_ENABLE I2C1CONbits.RCEN 00212 #define I2C_ACK_DATA I2C1CONbits.ACKDT 00213 #define I2C_ACK_SEQ_ENABLE I2C1CONbits.ACKEN 00214 00215 // 10/10/2011 2:14:02 PM removed TRIS/Data pins for SDA/SCL 00216 // 10/5/2011 10:42:28 AM bits not needed in p32 00217 /********************************************************************** 00218 * LCD 00219 **********************************************************************/ 00220 #define LCD_RS LATEbits.LATE9 00221 #define LCD_RS_TRIS TRISEbits.TRISE9 00222 00223 #define LCD_ENABLE LATBbits.LATB5 00224 #define LCD_ENABLE_TRIS TRISBbits.TRISB5 00225 00226 #define LCD_D0 LATEbits.LATE0 00227 #define LCD_D1 LATEbits.LATE1 00228 #define LCD_D2 LATEbits.LATE2 00229 #define LCD_D3 LATEbits.LATE3 00230 00231 #define LCD_D0_TRIS TRISEbits.TRISE0 00232 #define LCD_D1_TRIS TRISEbits.TRISE1 00233 #define LCD_D2_TRIS TRISEbits.TRISE2 00234 #define LCD_D3_TRIS TRISEbits.TRISE3 00235 00236 /********************************************************************** 00237 * mTouch 00238 **********************************************************************/ 00239 #define EDF_CapTouchGetButtonState(i) 0//MTouchGetButtonState(i) 00240 #define EDF_MTOUCH_PRESSED 1 00241 /****************************************************************************** 00242 * PTP 00243 * *****************************************************************************/ 00244 #define PTP1_LAT LATGbits.LATG15 00245 #define PTP2_LAT LATAbits.LATA0 00246 #define PTP3_LAT LATEbits.LATE4 00247 #define PTP4_LAT LATEbits.LATE5 00248 #define PTP5_LAT LATEbits.LATE6 00249 #define PTP6_LAT LATEbits.LATE7 00250 #define PTP7_LAT LATGbits.LATG9 00251 #define PTP8_LAT LATGbits.LATG1 00252 #define PTP9_LAT LATGbits.LATG0 00253 #define PTP10_LAT LATGbits.LATG14 00254 #define PTP11_LAT LATGbits.LATG12 00255 #define PTP12_LAT LATBbits.LATB12 00256 #define PTP13_LAT LATBbits.LATB13 00257 #define PTP14_LAT // NOT AVAILABLE 00258 #define PTP15_LAT // NOT AVAILABLE 00259 #define PTP16_LAT LATDbits.LATD14 00260 #define PTP17_LAT LATDbits.LATD15 00261 #define PTP18_LAT LATBbits.LATB14 00262 #define PTP19_LAT LATBbits.LATB15 00263 #define PTP20_LAT LATEbits.LATE8 00264 #define PTP21_LAT LATGbits.LATG13 00265 00266 #define PTP1_TRIS TRISGbits.TRISG15 00267 #define PTP2_TRIS TRISAbits.TRISA0 00268 #define PTP3_TRIS TRISEbits.TRISE4 00269 #define PTP4_TRIS TRISEbits.TRISE5 00270 #define PTP5_TRIS TRISEbits.TRISE6 00271 #define PTP6_TRIS TRISEbits.TRISE7 00272 #define PTP7_TRIS TRISGbits.TRISG9 00273 #define PTP8_TRIS TRISGbits.TRISG1 00274 #define PTP9_TRIS TRISGbits.TRISG0 00275 #define PTP10_TRIS TRISGbits.TRISG14 00276 #define PTP11_TRIS TRISGbits.TRISG12 00277 #define PTP12_TRIS TRISBbits.TRISB12 00278 #define PTP13_TRIS TRISBbits.TRISB13 00279 #define PTP14_TRIS // NOT AVAILABLE 00280 #define PTP15_TRIS // NOT AVAILABLE 00281 #define PTP16_TRIS TRISDbits.TRISD14 00282 #define PTP17_TRIS TRISDbits.TRISD15 00283 #define PTP18_TRIS TRISBbits.TRISB14 00284 #define PTP19_TRIS TRISBbits.TRISB15 00285 #define PTP20_TRIS TRISEbits.TRISE8 00286 #define PTP21_TRIS TRISGbits.TRISG13 00287 00288 #define PTP1_PORT PORTGbits.RG15 00289 #define PTP2_PORT PORTAbits.RA0 00290 #define PTP3_PORT PORTEbits.RE4 00291 #define PTP4_PORT PORTEbits.RE5 00292 #define PTP5_PORT PORTEbits.RE6 00293 #define PTP6_PORT PORTEbits.RE7 00294 #define PTP7_PORT PORTGbits.RG9 00295 #define PTP8_PORT PORTGbits.RG1 00296 #define PTP9_PORT PORTGbits.RG0 00297 #define PTP10_PORT PORTGbits.RG14 00298 #define PTP11_PORT PORTGbits.RG12 00299 #define PTP12_PORT PORTBbits.RB12 00300 #define PTP13_PORT PORTBbits.RB13 00301 #define PTP14_PORT // NOT AVAILABLE 00302 #define PTP15_PORT // NOT AVAILABLE 00303 #define PTP16_PORT PORTDbits.RD14 00304 #define PTP17_PORT PORTDbits.RD15 00305 #define PTP18_PORT PORTBbits.RB14 00306 #define PTP19_PORT PORTBbits.RB15 00307 #define PTP20_PORT PORTEbits.RE8 00308 #define PTP21_PORT PORTGbits.RG13 00309 00310 00311 00312 00313 #endif //__BSP_H