EDF - OnePIC MCU  v1.1.0
source/16bit/include/bsp.h
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00001 
00016 #ifndef __BSP_H
00017 #define __BSP_H
00018 #include <stdlib.h>
00019 #include <stdint.h>
00020 #include <stdio.h>
00021 #include "mTouch.h"
00022 #include <p24Fxxxx.h>
00023 
00024 #define LED_ON  1
00025 #define LED_OFF 0
00026 
00027 #define GetSystemClock()            16000000UL
00028 #define GetPeripheralClock()        16000000UL
00029 #define GetInstructionClock()       (GetSystemClock() / 2) 
00030 
00031 /**********************************************************************
00032 * LEDs
00033 **********************************************************************/
00034 #define gpLED_1_TRIS         TRISFbits.TRISF3
00035 #define gpLED_2_TRIS         TRISFbits.TRISF2
00036 #define gpLED_3_TRIS         TRISFbits.TRISF6
00037 #define gpLED_4_TRIS         TRISDbits.TRISD8
00038 #define gpLED_5_TRIS         TRISDbits.TRISD9
00039 #define gpLED_6_TRIS         TRISDbits.TRISD10
00040 #define gpLED_7_TRIS         TRISDbits.TRISD11
00041 #define gpLED_8_TRIS         TRISDbits.TRISD0
00042 
00043 #define gpLED_1              LATFbits.LATF3
00044 #define gpLED_2              LATFbits.LATF2
00045 #define gpLED_3              LATFbits.LATF6
00046 #define gpLED_4              LATDbits.LATD8
00047 #define gpLED_5              LATDbits.LATD9
00048 #define gpLED_6              LATDbits.LATD10
00049 #define gpLED_7              LATDbits.LATD11
00050 #define gpLED_8              LATDbits.LATD0
00051 
00052 #define gpLED_DOWN_TRIS    TRISGbits.TRISG9 
00053 #define gpLED_LEFT_TRIS    TRISGbits.TRISG7 
00054 #define gpLED_RIGHT_TRIS   TRISGbits.TRISG8 
00055 #define gpLED_UP_TRIS      TRISGbits.TRISG6 
00056 
00057 #define gpLED_DOWN           LATGbits.LATG9 
00058 #define gpLED_LEFT           LATGbits.LATG7 
00059 #define gpLED_RIGHT          LATGbits.LATG8 
00060 #define gpLED_UP             LATGbits.LATG6 
00061 
00062 /**********************************************************************
00063 * Switch
00064 **********************************************************************/
00065 
00066 #define SW1_TRIS        gpLED_1_TRIS 
00067 #define SW1_PORT         PORTFbits.RF3 
00068 #define SW1_LATCH        LATFbits.LATF3 
00070 /**********************************************************************
00071 * I2C
00072 **********************************************************************/
00073 
00074 #define I2C_MODULE_ENABLE               I2C1CONbits.I2CEN
00075 #define I2C_DISABLE_SLEW_CONTROL        I2C1CONbits.DISSLW
00076 #define I2C_INTERRUPT_FLAG              IFS1bits.MI2C1IF
00077 #define I2C_INTERRUPT_ENABLE            IEC1bits.MI2C1IE
00078 #define I2C_BRG                         I2C1BRG
00079 #define I2C_BCL_MASTER_BUS_COLLISION    I2C1STATbits.BCL
00080 #define I2C_SEN_START_CONDITION_ENABLE  I2C1CONbits.SEN
00081 #define I2C_TRANSMIT_REGISTER           I2C1TRN
00082 #define I2C_RECIEVE_REGISTER            I2C1RCV
00083 #define I2C_REPEATED_START_ENABLE       I2C1CONbits.RSEN
00084 #define I2C_ACK_STATUS                  I2C1STATbits.ACKSTAT
00085 #define I2C_STOP_CONDITION_ENABLE       I2C1CONbits.PEN
00086 #define I2C_RECIEVE_ENABLE              I2C1CONbits.RCEN
00087 #define I2C_ACK_DATA                    I2C1CONbits.ACKDT
00088 #define I2C_ACK_SEQ_ENABLE              I2C1CONbits.ACKEN
00089 
00090 /**********************************************************************
00091 * LCD
00092 **********************************************************************/
00093 
00094 #define LCD_RS              LATFbits.LATF1
00095 #define LCD_RS_TRIS             TRISFbits.TRISF1
00096     
00097 #define LCD_ENABLE          LATFbits.LATF0
00098 #define LCD_ENABLE_TRIS     TRISFbits.TRISF0
00099 
00100 #define LCD_D0              LATEbits.LATE0
00101 #define LCD_D1              LATEbits.LATE1
00102 #define LCD_D2              LATEbits.LATE2
00103 #define LCD_D3              LATEbits.LATE3
00104 
00105 #define LCD_D0_TRIS         TRISEbits.TRISE0
00106 #define LCD_D1_TRIS         TRISEbits.TRISE1
00107 #define LCD_D2_TRIS         TRISEbits.TRISE2
00108 #define LCD_D3_TRIS         TRISEbits.TRISE3
00109 
00110 /******************************************************************************
00111 * ADC
00112 ******************************************************************************/
00113 #define ADC_BUFFER                              ADC1BUF0
00114 #define ADC_OPERATING_MODE      AD1CONbits.ADON
00115 #define ADC_STOP_IN_IDLE        AD1CONbits.ADSIDL
00116 #define ADC_DATA_OUTPUT_FORMAT  AD1CONbits.FORM
00117 #define ADC_CONV_SOURCE         AD1CONbits.SSRC
00118 #define ADC_AUTO_SAMPLE         AD1CONbits.ASAM
00119 #define ADC_SAMPLE_ENABLE       AD1CONbits.SAMP
00120 #define ADC_CONV_DONE           AD1CONbits.DONE
00121 
00122 #define ADC_VOLTAGE_REF_CONFIG  AD1CON2bits.VCFG
00123 #define ADC_MUX_A_CH_SEL        AD1CON2bits.CSCNA
00124 #define ADC_BUFFER_FILL_STAT    AD1CON2bits.BUFS
00125 #define ADC_SAMPLE_SEQ_INT_SEL  AD1CON2bits.SMPI
00126 #define ADC_BUFFER_MODE_SEL     AD1CON2bits.BUFM
00127 #define ADC_ALT_SAMPLE_MODE     AD1CON2bits.ALTS
00128 
00129 #define ADC_CONV_CLK_SRC        AD1CON2bits.ADRC
00130 #define ADC_AUTO_SAMPLE_TIME    AD1CON2bits.SAMC
00131 #define ADC_CONV_CLK_PERIOD_SEL AD1CON2bits.ADCS
00132 
00133 /*** POT   RB8 AN8 ***********************************************************/
00134 #define ADC_POT_IO_BIT      8
00135 #define ADC_POT_IO_CH_BIT   8
00136 #define ADC_POT_LATCH       LATB
00137 #define ADC_POT_TRIS        TRISB
00138 /*** MIC   RB9 AN9 ***********************************************************/
00139 #define ADC_MIC_IO_BIT      9
00140 #define ADC_MIC_IO_CH_BIT   9
00141 #define ADC_POT_LATCH       LATB
00142 #define ADC_POT_TRIS        TRISB
00143 /*** UP    RB3 AN3 ***********************************************************/
00144 #define ADC_UP_IO_BIT       3
00145 #define ADC_UP_IO_CH_BIT    3
00146 #define ADC_POT_LATCH       LATB
00147 #define ADC_POT_TRIS        TRISB
00148 /*** DOWN  RB0 AN0 ***********************************************************/
00149 #define ADC_DOWN_IO_BIT     0
00150 #define ADC_DOWN_IO_CH_BIT  0
00151 #define ADC_POT_LATCH       LATB
00152 #define ADC_POT_TRIS        TRISB
00153 /*** LEFT  RB4 AN4 ***********************************************************/
00154 #define ADC_LEFT_IO_BIT     4
00155 #define ADC_LEFT_IO_CH_BIT  4
00156 #define ADC_POT_LATCH       LATB
00157 #define ADC_POT_TRIS        TRISB
00158 /*** RIGHT RB1 AN1 ***********************************************************/
00159 #define ADC_RIGHT_IO_BIT     1   
00160 #define ADC_RIGHT_IO_CH_BIT  1  
00161 #define ADC_POT_LATCH       LATB
00162 #define ADC_POT_TRIS        TRISB
00163 /*** ENTER RB2 AN2 ***********************************************************/
00164 #define ADC_ENTER_IO_BIT     2   
00165 #define ADC_ENTER_IO_CH_BIT  2  
00166 #define ADC_POT_LATCH       LATB
00167 #define ADC_POT_TRIS        TRISB
00168 
00169 /**********************************************************************
00170 * mTouch
00171 **********************************************************************/
00172 #define EDF_CapTouchGetButtonState(i)  MTouchGetButtonState(i)
00173 #define EDF_MTOUCH_PRESSED  MTOUCH_PRESSED
00174 // 10/5/2011 10:45:12 AM Make tri-state defines consistent -> all caps.
00175 // -> DONE 10/5/2011 1:26:52 PM
00176 // 10/5/2011 10:50:50 AM change LCD_D0:7 -> LCD_D0:3
00177 // -> DONE 10/5/2011 1:27:01 PM
00178 
00179 /******************************************************************************
00180 * USART
00181 ******************************************************************************/
00182 
00183 // XXX 10/5/2011 11:01:47 AM: TX/RX
00184 // RD3:RP22 TX
00185 // RD4:RP25 RX
00186 #define UART1_ENABLE                    U1MODEbits.UARTEN
00187 #define UART1_FREEZE                    U1MODEbits.UFRZ
00188 #define UART1_STOP_IN_IDLE              U1MODEbits.USIDL
00189 #define UART1_IRDA_ENABLE               U1MODEbits.IREN
00190 #define UART1_RTS_SEL                   U1MODEbits.RTSMD
00191 #define UART1_ALT_IO                    U1MODEbits.ALTIO
00192 #define UART1_ENABLE_BITS               U1MODEbits.UEN
00193 #define UART1_WAKE_ENABLE               U1MODEbits.WAKE
00194 #define UART1_LOOPBACK_SEL              U1MODEbits.LPBACK
00195 #define UART1_AUTO_BAUD_ENABLE          U1MODEbits.ABAUD
00196 #define UART1_RX_INV                    U1MODEbits.RXINV
00197 #define UART1_HIGH_BAUD_SEL             U1MODEbits.BRGH
00198 #define UART1_PARITY_DATA_SEL           U1MODEbits.PDSEL
00199 #define UART1_STOP_SEL                  U1MODEbits.STSEL
00200 
00201 #define UART1_TX_INT_SEL                U1STAbits.UTXISEL
00202 #define UART1_TX_POL_INV                U1STAbits.UTXINV
00203 #define UART1_TX_BREAK                  U1STAbits.UTXBRK
00204 #define UART1_TX_ENABLE                 U1STAbits.UTXEN
00205 #define UART1_TX_BUFFER_FULL            U1STAbits.UTXBF
00206 #define UART1_TX_SHIFT_REG_EMPTY        U1STAbits.TRMT
00207 #define UART1_ADDR_CHAR_DETECT          U1STAbits.ADDEN
00208 #define UART1_RX_IDLE                   U1STAbits.RIDLE
00209 #define UART1_PARITY_ERROR              U1STAbits.PERR
00210 #define UART1_FRAMING_ERROR             U1STAbits.FERR
00211 #define UART1_RX_BUFFER_OVERRUN_ERROR   U1STAbits.OERR
00212 #define UART1_TX_BUFFER_DATA_AVAILABLE  U1STAbits.URXDA
00213 
00214 #define UART1_TX_REG                    U1RXREG
00215 #define UART1_RX_REG                    U1TXREG
00216 #define UART1_BAUD_RATE                 U1BRG
00217 
00218 
00219 
00220 // XXX 10/5/2011 11:02:55 AM: Speaker
00221 /******************************************************************************
00222 * PWM - Controls Speaker/Buzzer
00223 ******************************************************************************/
00224 
00225 /*** PWM Registers ************************************************************/  
00226 
00227 #define OC1_STOP_OC_IN_IDLE     OC1CON1bits.OCSIDL
00228 #define OC1_OC_TMR_SEL          OC1CON1bits.OCTSEL
00229 #define OC1_TRIGGER_STATUS_SEL  OC1CON1bits.TRIGMODE
00230 #define OC1_OC_MODE_SEL         OC1CON1bits.OCM
00231 
00232 #define OC1_OCMP_INVERT         OC1CON2bits.OCINV
00233 #define OC1_CASCADE_ENABLE      OC1CON2bits.OC32
00234 #define OC1_TRIGGER_SYNC_SEL    OC1CON2bits.OCTRIG
00235 #define OC1_TRIGGER_STATUS      OC1CON2bits.TRIGSTAT
00236 #define OC1_PIN_DIRECTION_SEL   OC1CON2bits.OCTRIS
00237 #define OC1_SYNCSEL             OC1CON2bits.SYNCSEL
00238 
00239 /*** TMR 1 ********************************************************************/  
00240 #define TMR1_PERIOD         PR1
00241 #define TMR1_ON             T1CONbits.TON
00242 #define TMR1_STOP_IN_IDLE   T1CONbits.TSIDL
00243 #define TMR1_GATE_ENABLE    T1CONbits.TGATE
00244 #define TMR1_CLK_PRESCALE   T1CONbits.TCKPS   
00245 #define TMR1_EXT_CLK_SYNC   T1CONbits.TSYNC
00246 #define TMR1_CLK_SRC        T1CONbits.TCS
00247 /*** TMR 2/4 ******************************************************************/ 
00248 
00249 #define TMR2_PERIOD         PR2
00250 #define TMR2_ON             T2CONbits.TON
00251 #define TMR2_STOP_IN_IDLE   T2CONbits.TSIDL
00252 #define TMR2_GATE_ENABLE    T2CONbits.TGATE
00253 #define TMR2_CLK_PRESCALE   T2CONbits.TCKPS   
00254 #define TMR2_32_BIT_MODE    T2CONbits.T32
00255 #define TMR2_CLK_SRC        T2CONbits.TCS
00256 
00257 #define TMR4_PERIOD         PR4
00258 #define TMR4_ON             T4CONbits.TON
00259 #define TMR4_STOP_IN_IDLE   T4CONbits.TSIDL
00260 #define TMR4_GATE_ENABLE    T4CONbits.TGATE
00261 #define TMR4_CLK_PRESCALE   T4CONbits.TCKPS   
00262 #define TMR4_32_BIT_MODE    T4CONbits.T32
00263 #define TMR4_CLK_SRC        T4CONbits.TCS
00264 /*** TMR 3/5 ******************************************************************/ 
00265 #define TMR3_PERIOD         PR3
00266 #define TMR3_ON             T3CONbits.TON
00267 #define TMR3_STOP_IN_IDLE   T3CONbits.TSIDL
00268 #define TMR3_GATE_ENABLE    T3CONbits.TGATE
00269 #define TMR3_CLK_PRESCALE   T3CONbits.TCKPS   
00270 #define TMR3_CLK_SRC        T3CONbits.TCS
00271 
00272 #define TMR5_PERIOD         PR5
00273 #define TMR5_ON             T5CONbits.TON
00274 #define TMR5_STOP_IN_IDLE   T5CONbits.TSIDL
00275 #define TMR5_GATE_ENABLE    T5CONbits.TGATE
00276 #define TMR5_CLK_PRESCALE   T5CONbits.TCKPS   
00277 #define TMR5_CLK_SRC        T5CONbits.TCS
00278 
00279 // XXX 10/5/2011 11:05:32 AM: Add Buzzer
00280 // RD5/RP20
00281 // DONE -> PWM added. 10/10/2011 4:44:13 PM
00282 
00283 /******************************************************************************
00284 * SPI
00285 ******************************************************************************/
00286 
00287 // XXX 10/5/2011 11:09:57 AM: Add SPI
00288 // 10/10/2011 10:56:00 AM: DONE
00289 #define SPI1_BUFFER             SPI1BUF
00290 #define SPI1_ENABLE             SPI1STATbits.SPIEN
00291 #define SPI1_STOP_IN_IDLE       SPI1STATbits.PISIDL
00292 #define SPI1_BUFFER_ELEMENT_CNT SPI1STATbits.SPIBEC
00293 #define SPI1_SR_EMPTY           SPI1STATbits.SRMPT
00294 #define SPI1_RX_OVERFLOW        SPI1STATbits.SPIROV
00295 #define SPI1_RX_FIFO_EMPTY      SPI1STATbits.SRXMPT
00296 #define SPI1_INT_MODE_SEL       SPI1STATbits.SISEL
00297 #define SPI1_TX_BUFFER_FULL     SPI1STATbits.SPITBF
00298 #define SPI1_RX_BUFFER_FULL     SPI1STATbits.SPIRBF
00299 
00300 #define SPI1_SCK_DISABLE     SPI1CON1bits.DISSCK
00301 #define SPI1_SDO_DISABLE     SPI1CON1bits.DISSDO
00302 #define SPI1_MODE16_SEL      SPI1CON1bits.MODE16
00303 #define SPI1_SAMPLE_PHASE    SPI1CON1bits.SMP
00304 #define SPI1_CLK_EDGE_SEL    SPI1CON1bits.CKE
00305 #define SPI1_SS_ENABLE       SPI1CON1bits.SSEN
00306 #define SPI1_CLK_POL_SEL     SPI1CON1bits.CKP
00307 #define SPI1_MASTER_ENABLE   SPI1CON1bits.MSTEN
00308 #define SPI1_SEC_PRESCALE    SPI1CON1bits.SPRE
00309 #define SPI1_PRI_PRESCALE    SPI1CON1bits.PPRE
00310     
00311 #define SPI1_FRAMED_MODE_ENABLE      SPI1CON2bits.FRMEN
00312 #define SPI1_FRAME_SYNC_PULSE_DIR    SPI1CON2bits.SPIFSD
00313 #define SPI1_FRAME_SYNC_PULSE_POL    SPI1CON2bits.SPIFPOL
00314 #define SPI1_FRAME_SYNC_PULSE_EDGE   SPI1CON2bits.SPIFE
00315 #define SPI1_ENHANCE_BUFFER_ENABLE   SPI1CON2bits.SPIBEN
00316 
00317 /******************************************************************************
00318 * PIC Tail Plus
00319 ******************************************************************************/
00320 
00321 // XXX 10/5/2011 1:23:18 PM: PTP
00322 // list all PORT/LAT/TRIS
00323 // DONE -> 10/5/2011 3:54:55 PM
00324 #define PTP1_LAT    LATBbits.RB10
00325 #define PTP2_LAT    LATBbits.RB11
00326 #define PTP3_LAT    LATBbits.RB12
00327 #define PTP4_LAT    LATBbits.RB13
00328 #define PTP5_LAT    LATBbits.RB14
00329 #define PTP6_LAT    LATBbits.RB15
00330 #define PTP7_LAT    // NOT AVAILABLE ON P24
00331 #define PTP8_LAT    // NOT AVAILABLE ON P24
00332 #define PTP9_LAT    // NOT AVAILABLE ON P24
00333 #define PTP10_LAT   // NOT AVAILABLE ON P24
00334 #define PTP11_LAT   // NOT AVAILABLE ON P24
00335 #define PTP12_LAT   LATDbits.RD6
00336 #define PTP13_LAT   LATDbits.RD7
00337 #define PTP14_LAT   LATCbits.RC14
00338 #define PTP15_LAT   LATCbits.RC15
00339 #define PTP16_LAT   LATCbits.RC16
00340 #define PTP17_LAT   LATEbits.RE4
00341 #define PTP18_LAT   // NOT AVAILABLE ON P24
00342 #define PTP19_LAT   LATEbits.RE6
00343 #define PTP20_LAT   LATEbits.RE5
00344 #define PTP21_LAT   LATEbits.RE7
00345 
00346 #define PTP1_PORT    PORTBbits.RB10
00347 #define PTP2_PORT    PORTBbits.RB11
00348 #define PTP3_PORT    PORTBbits.RB12
00349 #define PTP4_PORT    PORTBbits.RB13
00350 #define PTP5_PORT    PORTBbits.RB14
00351 #define PTP6_PORT    PORTBbits.RB15
00352 #define PTP7_PORT    // NOT AVAILABLE ON P24
00353 #define PTP8_PORT    // NOT AVAILABLE ON P24
00354 #define PTP9_PORT    // NOT AVAILABLE ON P24
00355 #define PTP10_PORT   // NOT AVAILABLE ON P24
00356 #define PTP11_PORT   // NOT AVAILABLE ON P24
00357 #define PTP12_PORT   PORTDbits.RD6
00358 #define PTP13_PORT   PORTDbits.RD7
00359 #define PTP14_PORT   PORTCbits.RC14
00360 #define PTP15_PORT   PORTCbits.RC15
00361 #define PTP16_PORT   PORTCbits.RC16
00362 #define PTP17_PORT   PORTEbits.RE4
00363 #define PTP18_PORT   // NOT AVAILABLE ON P24
00364 #define PTP19_PORT   PORTEbits.RE6
00365 #define PTP20_PORT   PORTEbits.RE5
00366 #define PTP21_PORT   PORTEbits.RE7
00367 
00368 #define PTP1_TRIS    TRISBbits.TRISB10
00369 #define PTP2_TRIS    TRISBbits.TRISB11
00370 #define PTP3_TRIS    TRISBbits.TRISB12
00371 #define PTP4_TRIS    TRISBbits.TRISB13
00372 #define PTP5_TRIS    TRISBbits.TRISB14
00373 #define PTP6_TRIS    TRISBbits.TRISB15
00374 #define PTP7_TRIS    // NOT AVAILABLE ON P24
00375 #define PTP8_TRIS    // NOT AVAILABLE ON P24
00376 #define PTP9_TRIS    // NOT AVAILABLE ON P24
00377 #define PTP10_TRIS   // NOT AVAILABLE ON P24
00378 #define PTP11_TRIS   // NOT AVAILABLE ON P24
00379 #define PTP12_TRIS   TRISDbits.TRISD6
00380 #define PTP13_TRIS   TRISDbits.TRISD7
00381 #define PTP14_TRIS   TRISCbits.TRISC14
00382 #define PTP15_TRIS   TRISCbits.TRISC15
00383 #define PTP16_TRIS   TRISCbits.TRISC16
00384 #define PTP17_TRIS   TRISEbits.TRISE4
00385 #define PTP18_TRIS   // NOT AVAILABLE ON P24
00386 #define PTP19_TRIS   TRISEbits.TRISE6
00387 #define PTP20_TRIS   TRISEbits.TRISE5
00388 #define PTP21_TRIS   TRISEbits.TRISE7
00389 
00390 #endif //_BSP_H
00391