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EDF - OnePIC MCU
v1.1.0
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EDF - OnePIC MCU
v1.1.0
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all board specifics are defined in here: More...
#include <stdlib.h>#include <stdint.h>#include <stdio.h>#include "mTouch.h"#include <p24Fxxxx.h>
Go to the source code of this file.
Defines | |
| #define | LED_ON 1 |
| #define | LED_OFF 0 |
| #define | GetSystemClock() 16000000UL |
| #define | GetPeripheralClock() 16000000UL |
| #define | GetInstructionClock() (GetSystemClock() / 2) |
| #define | gpLED_1_TRIS TRISFbits.TRISF3 |
| #define | gpLED_2_TRIS TRISFbits.TRISF2 |
| #define | gpLED_3_TRIS TRISFbits.TRISF6 |
| #define | gpLED_4_TRIS TRISDbits.TRISD8 |
| #define | gpLED_5_TRIS TRISDbits.TRISD9 |
| #define | gpLED_6_TRIS TRISDbits.TRISD10 |
| #define | gpLED_7_TRIS TRISDbits.TRISD11 |
| #define | gpLED_8_TRIS TRISDbits.TRISD0 |
| #define | gpLED_1 LATFbits.LATF3 |
| #define | gpLED_2 LATFbits.LATF2 |
| #define | gpLED_3 LATFbits.LATF6 |
| #define | gpLED_4 LATDbits.LATD8 |
| #define | gpLED_5 LATDbits.LATD9 |
| #define | gpLED_6 LATDbits.LATD10 |
| #define | gpLED_7 LATDbits.LATD11 |
| #define | gpLED_8 LATDbits.LATD0 |
| #define | gpLED_DOWN_TRIS TRISGbits.TRISG9 |
| #define | gpLED_LEFT_TRIS TRISGbits.TRISG7 |
| #define | gpLED_RIGHT_TRIS TRISGbits.TRISG8 |
| #define | gpLED_UP_TRIS TRISGbits.TRISG6 |
| #define | gpLED_DOWN LATGbits.LATG9 |
| #define | gpLED_LEFT LATGbits.LATG7 |
| #define | gpLED_RIGHT LATGbits.LATG8 |
| #define | gpLED_UP LATGbits.LATG6 |
| #define | SW1_TRIS gpLED_1_TRIS |
| shared with LED1 | |
| #define | SW1_PORT PORTFbits.RF3 |
| #define | SW1_LATCH LATFbits.LATF3 |
| #define | I2C_MODULE_ENABLE I2C1CONbits.I2CEN |
| #define | I2C_DISABLE_SLEW_CONTROL I2C1CONbits.DISSLW |
| #define | I2C_INTERRUPT_FLAG IFS1bits.MI2C1IF |
| #define | I2C_INTERRUPT_ENABLE IEC1bits.MI2C1IE |
| #define | I2C_BRG I2C1BRG |
| #define | I2C_BCL_MASTER_BUS_COLLISION I2C1STATbits.BCL |
| #define | I2C_SEN_START_CONDITION_ENABLE I2C1CONbits.SEN |
| #define | I2C_TRANSMIT_REGISTER I2C1TRN |
| #define | I2C_RECIEVE_REGISTER I2C1RCV |
| #define | I2C_REPEATED_START_ENABLE I2C1CONbits.RSEN |
| #define | I2C_ACK_STATUS I2C1STATbits.ACKSTAT |
| #define | I2C_STOP_CONDITION_ENABLE I2C1CONbits.PEN |
| #define | I2C_RECIEVE_ENABLE I2C1CONbits.RCEN |
| #define | I2C_ACK_DATA I2C1CONbits.ACKDT |
| #define | I2C_ACK_SEQ_ENABLE I2C1CONbits.ACKEN |
| #define | LCD_RS LATFbits.LATF1 |
| #define | LCD_RS_TRIS TRISFbits.TRISF1 |
| #define | LCD_ENABLE LATFbits.LATF0 |
| #define | LCD_ENABLE_TRIS TRISFbits.TRISF0 |
| #define | LCD_D0 LATEbits.LATE0 |
| #define | LCD_D1 LATEbits.LATE1 |
| #define | LCD_D2 LATEbits.LATE2 |
| #define | LCD_D3 LATEbits.LATE3 |
| #define | LCD_D0_TRIS TRISEbits.TRISE0 |
| #define | LCD_D1_TRIS TRISEbits.TRISE1 |
| #define | LCD_D2_TRIS TRISEbits.TRISE2 |
| #define | LCD_D3_TRIS TRISEbits.TRISE3 |
| #define | ADC_BUFFER ADC1BUF0 |
| #define | ADC_OPERATING_MODE AD1CONbits.ADON |
| #define | ADC_STOP_IN_IDLE AD1CONbits.ADSIDL |
| #define | ADC_DATA_OUTPUT_FORMAT AD1CONbits.FORM |
| #define | ADC_CONV_SOURCE AD1CONbits.SSRC |
| #define | ADC_AUTO_SAMPLE AD1CONbits.ASAM |
| #define | ADC_SAMPLE_ENABLE AD1CONbits.SAMP |
| #define | ADC_CONV_DONE AD1CONbits.DONE |
| #define | ADC_VOLTAGE_REF_CONFIG AD1CON2bits.VCFG |
| #define | ADC_MUX_A_CH_SEL AD1CON2bits.CSCNA |
| #define | ADC_BUFFER_FILL_STAT AD1CON2bits.BUFS |
| #define | ADC_SAMPLE_SEQ_INT_SEL AD1CON2bits.SMPI |
| #define | ADC_BUFFER_MODE_SEL AD1CON2bits.BUFM |
| #define | ADC_ALT_SAMPLE_MODE AD1CON2bits.ALTS |
| #define | ADC_CONV_CLK_SRC AD1CON2bits.ADRC |
| #define | ADC_AUTO_SAMPLE_TIME AD1CON2bits.SAMC |
| #define | ADC_CONV_CLK_PERIOD_SEL AD1CON2bits.ADCS |
| #define | ADC_POT_IO_BIT 8 |
| #define | ADC_POT_IO_CH_BIT 8 |
| #define | ADC_POT_LATCH LATB |
| #define | ADC_POT_TRIS TRISB |
| #define | ADC_MIC_IO_BIT 9 |
| #define | ADC_MIC_IO_CH_BIT 9 |
| #define | ADC_POT_LATCH LATB |
| #define | ADC_POT_TRIS TRISB |
| #define | ADC_UP_IO_BIT 3 |
| #define | ADC_UP_IO_CH_BIT 3 |
| #define | ADC_POT_LATCH LATB |
| #define | ADC_POT_TRIS TRISB |
| #define | ADC_DOWN_IO_BIT 0 |
| #define | ADC_DOWN_IO_CH_BIT 0 |
| #define | ADC_POT_LATCH LATB |
| #define | ADC_POT_TRIS TRISB |
| #define | ADC_LEFT_IO_BIT 4 |
| #define | ADC_LEFT_IO_CH_BIT 4 |
| #define | ADC_POT_LATCH LATB |
| #define | ADC_POT_TRIS TRISB |
| #define | ADC_RIGHT_IO_BIT 1 |
| #define | ADC_RIGHT_IO_CH_BIT 1 |
| #define | ADC_POT_LATCH LATB |
| #define | ADC_POT_TRIS TRISB |
| #define | ADC_ENTER_IO_BIT 2 |
| #define | ADC_ENTER_IO_CH_BIT 2 |
| #define | ADC_POT_LATCH LATB |
| #define | ADC_POT_TRIS TRISB |
| #define | EDF_CapTouchGetButtonState(i) MTouchGetButtonState(i) |
| #define | EDF_MTOUCH_PRESSED MTOUCH_PRESSED |
| #define | UART1_ENABLE U1MODEbits.UARTEN |
| #define | UART1_FREEZE U1MODEbits.UFRZ |
| #define | UART1_STOP_IN_IDLE U1MODEbits.USIDL |
| #define | UART1_IRDA_ENABLE U1MODEbits.IREN |
| #define | UART1_RTS_SEL U1MODEbits.RTSMD |
| #define | UART1_ALT_IO U1MODEbits.ALTIO |
| #define | UART1_ENABLE_BITS U1MODEbits.UEN |
| #define | UART1_WAKE_ENABLE U1MODEbits.WAKE |
| #define | UART1_LOOPBACK_SEL U1MODEbits.LPBACK |
| #define | UART1_AUTO_BAUD_ENABLE U1MODEbits.ABAUD |
| #define | UART1_RX_INV U1MODEbits.RXINV |
| #define | UART1_HIGH_BAUD_SEL U1MODEbits.BRGH |
| #define | UART1_PARITY_DATA_SEL U1MODEbits.PDSEL |
| #define | UART1_STOP_SEL U1MODEbits.STSEL |
| #define | UART1_TX_INT_SEL U1STAbits.UTXISEL |
| #define | UART1_TX_POL_INV U1STAbits.UTXINV |
| #define | UART1_TX_BREAK U1STAbits.UTXBRK |
| #define | UART1_TX_ENABLE U1STAbits.UTXEN |
| #define | UART1_TX_BUFFER_FULL U1STAbits.UTXBF |
| #define | UART1_TX_SHIFT_REG_EMPTY U1STAbits.TRMT |
| #define | UART1_ADDR_CHAR_DETECT U1STAbits.ADDEN |
| #define | UART1_RX_IDLE U1STAbits.RIDLE |
| #define | UART1_PARITY_ERROR U1STAbits.PERR |
| #define | UART1_FRAMING_ERROR U1STAbits.FERR |
| #define | UART1_RX_BUFFER_OVERRUN_ERROR U1STAbits.OERR |
| #define | UART1_TX_BUFFER_DATA_AVAILABLE U1STAbits.URXDA |
| #define | UART1_TX_REG U1RXREG |
| #define | UART1_RX_REG U1TXREG |
| #define | UART1_BAUD_RATE U1BRG |
| #define | OC1_STOP_OC_IN_IDLE OC1CON1bits.OCSIDL |
| #define | OC1_OC_TMR_SEL OC1CON1bits.OCTSEL |
| #define | OC1_TRIGGER_STATUS_SEL OC1CON1bits.TRIGMODE |
| #define | OC1_OC_MODE_SEL OC1CON1bits.OCM |
| #define | OC1_OCMP_INVERT OC1CON2bits.OCINV |
| #define | OC1_CASCADE_ENABLE OC1CON2bits.OC32 |
| #define | OC1_TRIGGER_SYNC_SEL OC1CON2bits.OCTRIG |
| #define | OC1_TRIGGER_STATUS OC1CON2bits.TRIGSTAT |
| #define | OC1_PIN_DIRECTION_SEL OC1CON2bits.OCTRIS |
| #define | OC1_SYNCSEL OC1CON2bits.SYNCSEL |
| #define | TMR1_PERIOD PR1 |
| #define | TMR1_ON T1CONbits.TON |
| #define | TMR1_STOP_IN_IDLE T1CONbits.TSIDL |
| #define | TMR1_GATE_ENABLE T1CONbits.TGATE |
| #define | TMR1_CLK_PRESCALE T1CONbits.TCKPS |
| #define | TMR1_EXT_CLK_SYNC T1CONbits.TSYNC |
| #define | TMR1_CLK_SRC T1CONbits.TCS |
| #define | TMR2_PERIOD PR2 |
| #define | TMR2_ON T2CONbits.TON |
| #define | TMR2_STOP_IN_IDLE T2CONbits.TSIDL |
| #define | TMR2_GATE_ENABLE T2CONbits.TGATE |
| #define | TMR2_CLK_PRESCALE T2CONbits.TCKPS |
| #define | TMR2_32_BIT_MODE T2CONbits.T32 |
| #define | TMR2_CLK_SRC T2CONbits.TCS |
| #define | TMR4_PERIOD PR4 |
| #define | TMR4_ON T4CONbits.TON |
| #define | TMR4_STOP_IN_IDLE T4CONbits.TSIDL |
| #define | TMR4_GATE_ENABLE T4CONbits.TGATE |
| #define | TMR4_CLK_PRESCALE T4CONbits.TCKPS |
| #define | TMR4_32_BIT_MODE T4CONbits.T32 |
| #define | TMR4_CLK_SRC T4CONbits.TCS |
| #define | TMR3_PERIOD PR3 |
| #define | TMR3_ON T3CONbits.TON |
| #define | TMR3_STOP_IN_IDLE T3CONbits.TSIDL |
| #define | TMR3_GATE_ENABLE T3CONbits.TGATE |
| #define | TMR3_CLK_PRESCALE T3CONbits.TCKPS |
| #define | TMR3_CLK_SRC T3CONbits.TCS |
| #define | TMR5_PERIOD PR5 |
| #define | TMR5_ON T5CONbits.TON |
| #define | TMR5_STOP_IN_IDLE T5CONbits.TSIDL |
| #define | TMR5_GATE_ENABLE T5CONbits.TGATE |
| #define | TMR5_CLK_PRESCALE T5CONbits.TCKPS |
| #define | TMR5_CLK_SRC T5CONbits.TCS |
| #define | SPI1_BUFFER SPI1BUF |
| #define | SPI1_ENABLE SPI1STATbits.SPIEN |
| #define | SPI1_STOP_IN_IDLE SPI1STATbits.PISIDL |
| #define | SPI1_BUFFER_ELEMENT_CNT SPI1STATbits.SPIBEC |
| #define | SPI1_SR_EMPTY SPI1STATbits.SRMPT |
| #define | SPI1_RX_OVERFLOW SPI1STATbits.SPIROV |
| #define | SPI1_RX_FIFO_EMPTY SPI1STATbits.SRXMPT |
| #define | SPI1_INT_MODE_SEL SPI1STATbits.SISEL |
| #define | SPI1_TX_BUFFER_FULL SPI1STATbits.SPITBF |
| #define | SPI1_RX_BUFFER_FULL SPI1STATbits.SPIRBF |
| #define | SPI1_SCK_DISABLE SPI1CON1bits.DISSCK |
| #define | SPI1_SDO_DISABLE SPI1CON1bits.DISSDO |
| #define | SPI1_MODE16_SEL SPI1CON1bits.MODE16 |
| #define | SPI1_SAMPLE_PHASE SPI1CON1bits.SMP |
| #define | SPI1_CLK_EDGE_SEL SPI1CON1bits.CKE |
| #define | SPI1_SS_ENABLE SPI1CON1bits.SSEN |
| #define | SPI1_CLK_POL_SEL SPI1CON1bits.CKP |
| #define | SPI1_MASTER_ENABLE SPI1CON1bits.MSTEN |
| #define | SPI1_SEC_PRESCALE SPI1CON1bits.SPRE |
| #define | SPI1_PRI_PRESCALE SPI1CON1bits.PPRE |
| #define | SPI1_FRAMED_MODE_ENABLE SPI1CON2bits.FRMEN |
| #define | SPI1_FRAME_SYNC_PULSE_DIR SPI1CON2bits.SPIFSD |
| #define | SPI1_FRAME_SYNC_PULSE_POL SPI1CON2bits.SPIFPOL |
| #define | SPI1_FRAME_SYNC_PULSE_EDGE SPI1CON2bits.SPIFE |
| #define | SPI1_ENHANCE_BUFFER_ENABLE SPI1CON2bits.SPIBEN |
| #define | PTP1_LAT LATBbits.RB10 |
| #define | PTP2_LAT LATBbits.RB11 |
| #define | PTP3_LAT LATBbits.RB12 |
| #define | PTP4_LAT LATBbits.RB13 |
| #define | PTP5_LAT LATBbits.RB14 |
| #define | PTP6_LAT LATBbits.RB15 |
| #define | PTP7_LAT |
| #define | PTP8_LAT |
| #define | PTP9_LAT |
| #define | PTP10_LAT |
| #define | PTP11_LAT |
| #define | PTP12_LAT LATDbits.RD6 |
| #define | PTP13_LAT LATDbits.RD7 |
| #define | PTP14_LAT LATCbits.RC14 |
| #define | PTP15_LAT LATCbits.RC15 |
| #define | PTP16_LAT LATCbits.RC16 |
| #define | PTP17_LAT LATEbits.RE4 |
| #define | PTP18_LAT |
| #define | PTP19_LAT LATEbits.RE6 |
| #define | PTP20_LAT LATEbits.RE5 |
| #define | PTP21_LAT LATEbits.RE7 |
| #define | PTP1_PORT PORTBbits.RB10 |
| #define | PTP2_PORT PORTBbits.RB11 |
| #define | PTP3_PORT PORTBbits.RB12 |
| #define | PTP4_PORT PORTBbits.RB13 |
| #define | PTP5_PORT PORTBbits.RB14 |
| #define | PTP6_PORT PORTBbits.RB15 |
| #define | PTP7_PORT |
| #define | PTP8_PORT |
| #define | PTP9_PORT |
| #define | PTP10_PORT |
| #define | PTP11_PORT |
| #define | PTP12_PORT PORTDbits.RD6 |
| #define | PTP13_PORT PORTDbits.RD7 |
| #define | PTP14_PORT PORTCbits.RC14 |
| #define | PTP15_PORT PORTCbits.RC15 |
| #define | PTP16_PORT PORTCbits.RC16 |
| #define | PTP17_PORT PORTEbits.RE4 |
| #define | PTP18_PORT |
| #define | PTP19_PORT PORTEbits.RE6 |
| #define | PTP20_PORT PORTEbits.RE5 |
| #define | PTP21_PORT PORTEbits.RE7 |
| #define | PTP1_TRIS TRISBbits.TRISB10 |
| #define | PTP2_TRIS TRISBbits.TRISB11 |
| #define | PTP3_TRIS TRISBbits.TRISB12 |
| #define | PTP4_TRIS TRISBbits.TRISB13 |
| #define | PTP5_TRIS TRISBbits.TRISB14 |
| #define | PTP6_TRIS TRISBbits.TRISB15 |
| #define | PTP7_TRIS |
| #define | PTP8_TRIS |
| #define | PTP9_TRIS |
| #define | PTP10_TRIS |
| #define | PTP11_TRIS |
| #define | PTP12_TRIS TRISDbits.TRISD6 |
| #define | PTP13_TRIS TRISDbits.TRISD7 |
| #define | PTP14_TRIS TRISCbits.TRISC14 |
| #define | PTP15_TRIS TRISCbits.TRISC15 |
| #define | PTP16_TRIS TRISCbits.TRISC16 |
| #define | PTP17_TRIS TRISEbits.TRISE4 |
| #define | PTP18_TRIS |
| #define | PTP19_TRIS TRISEbits.TRISE6 |
| #define | PTP20_TRIS TRISEbits.TRISE5 |
| #define | PTP21_TRIS TRISEbits.TRISE7 |
all board specifics are defined in here:
Definition in file bsp.h.
1.7.5