先前參加台中場次的 masters 2019，活動中聆聽很多也學習到不少
會後購買了一片APP044板子接觸後有些不懂的地方，例如範例中使用DMA的技巧。
我在dsPIC33EP512MU810這DATASHEET看了一陣子還是有一些不懂的地方，還請前輩可以指導!
在文件中指出DPSRAM的空間分配為0xD00到0xE00 約4Kb的空間。
那麼範例中提到這個指令
__eds__ ECAN1MSGBUF ecan1msgBuf __attribute__((space(eds), aligned(ECAN1_MSG_BUF_LENGTH * 16)));
這是否是將上述的Buff建立在所謂DPSRAM而非RAM中
如果是這樣，建立在RAM和建立在DPSRAM對DMA的使用又甚麼差異呢?或是說是根據Device選擇建立在何處?
另外以下是對範例中的疑問
在CAN202C_V2_Ex5中的ECAN1使用DMA0做TX通道、使用DMA2做RX通道
那麼在此範例中是否只需要將Buff建為ECAN1_MSG_BUF_LENGTH = 2的二維空間即可，原範例中設定長度是否是因應can的32buff而規劃
#define ECAN1_MSG_BUF_LENGTH 32
typedef uint16_t ECAN1MSGBUF[ECAN1_MSG_BUF_LENGTH][8];
以下DMA的Buff配置就有待前輩指導觀念了
不知道我的理解是否正確
DMA0STAL = (uint16_t)(int_least24_t)(&ecan1msgBuf);
DMA0STAH = 0;
DMA2STAL = (uint16_t)(int_least24_t)(&ecan1msgBuf);
DMA2STAH = 0;
這兩個DMA Buff位置重疊應該修正DMA2STAH之offset值或是DMA2STAL取址在+8去修正
/******************************************************************************
* Function: void DMA0Init(void)
*
* PreCondition: None
*
* Input: None
*
* Output: None
*
* Side Effects: None
*
* Overview: DMA0 initialization/configuration function.
* Direction: Read from RAM and write to the C1TXD register
* AMODE: Peripheral Indirect Addressing mode
* MODE: Continuous, Ping-Pong modes disabled
* IRQ: ECAN1 Transmit Interrupt
*****************************************************************************/
void DMA0Init( void )
{
DMA0CON = 0x2020;
DMA0PAD = ( int ) &C1TXD; /* ECAN 1 (C1TXD) */
DMA0CNT = 0x0007;
DMA0REQ = 0x0046; /* ECAN 1 Transmit */
#ifdef _HAS_DMA_
DMA0STAL = __builtin_dmaoffset( ecan1msgBuf );
DMA0STAH = __builtin_dmapage( ecan1msgBuf );
#else
DMA0STAL = (uint16_t)(int_least24_t)(&ecan1msgBuf);
DMA0STAH = 0;
#endif
DMA0CONbits.CHEN = 1;
}
/******************************************************************************
* Function: void DMA2Init(void)
*
* PreCondition: None
*
* Input: None
*
* Output: None
*
* Side Effects: None
*
* Overview: DMA2 initialization/configuration function.
* Direction: Read from RAM and write to the C1RXD register
* AMODE: Peripheral Indirect Addressing mode
* MODE: Continuous, Ping-Pong modes disabled
* IRQ: ECAN1 Transmit Interrupt
*****************************************************************************/
void DMA2Init( void )
{
DMA2CON = 0x0020;
DMA2PAD = ( int ) &C1RXD; /* ECAN 2 (C1RXD) */
DMA2CNT = 0x0007;
DMA2REQ = 0x0022; /* ECAN 2 Receive */
#ifdef _HAS_DMA_
DMA2STAL = __builtin_dmaoffset( ecan1msgBuf );
DMA2STAH = __builtin_dmapage( ecan1msgBuf );
#else
DMA2STAL = (uint16_t)(int_least24_t)(&ecan1msgBuf);
DMA2STAH = 0;
#endif
DMA2CONbits.CHEN = 1;
}
最後想問在can接收設定中04、15、02 buffer在接收完成後都會跑到dma通道存到buff中，那指向ecan1msgBuf[index][0<=N<=7]的index(0<=index<=31)是由DMA2CNT的值來遞增(DMA2CNT=7即收滿8個C1RXD)Index
/******************************************************************************
* Function: void Ecan1Init(void)
*
* PreCondition: None
*
* Input: None
*
* Output: None
*
* Side Effects: None
*
* Overview: ECAN1 initialization function.This function is used to
* initialize the ECAN1 module by configuring the message
* buffers, and the acceptance filters and
* setting appropriate masks for the same.
*****************************************************************************/
void Ecan1Init( void )
{
/* Request Configuration Mode */
C1CTRL1bits.REQOP = 4;
while( C1CTRL1bits.OPMODE != 4 );
C1CTRL1bits.CANCKS = 1 ;
Ecan1ClkInit();
C1FCTRLbits.FSA = 0b01000; /* FIFO Starts at Message Buffer 8 */
C1FCTRLbits.DMABS = 0b100; /* 16 CAN Message Buffers in DMA RAM */
/* Filter Configuration
Ecan1WriteRxAcptFilter(int n, long identifier, unsigned int exide,unsigned int bufPnt,unsigned int maskSel)
n = 0 to 15 -> Filter number
identifier -> SID <10:0> : EID <17:0>
exide = 0 -> Match messages with standard identifier addresses
exide = 1 -> Match messages with extended identifier addresses
bufPnt = 0 to 14 -> RX Buffer 0 to 14
bufPnt = 15 -> RX FIFO Buffer
maskSel = 0 -> Acceptance Mask 0 register contains mask
maskSel = 1 -> Acceptance Mask 1 register contains mask
maskSel = 2 -> Acceptance Mask 2 register contains mask
maskSel = 3 -> No Mask Selection
*/
Ecan1WriteRxAcptFilter( 1, (0x00 | EXT_CLOCK_ID), 0, 04, 1 ); // Filter 1
Ecan1WriteRxAcptFilter( 2, (0x00 | EXT_VR1_ID ) , 0, 15, 1 ); // Filter 2
Ecan1WriteRxAcptFilter( 0, 0x200 , 0, 02, 0 ); // Filter 0 point to Buffer0 in order to response to Remote Transfer request - Exercise 5
/* Mask Configuration
Ecan1WriteRxAcptMask(int m, long identifierMask, unsigned int mide, unsigned int exide)
m = 0 to 2 -> Mask Number
identifier -> SID <10:0> : EID <17:0>
mide = 0 -> Match either standard or extended address message if filters match
mide = 1 -> Match only message types that correpond to 'exide' bit in filter
exide = 0 -> Match messages with standard identifier addresses
exide = 1 -> Match messages with extended identifier addresses
*/
Ecan1WriteRxAcptMask( 1, 0x1FFFFFFF, 1, 0 );
Ecan1WriteRxAcptMask( 0, 0x1FFFFFFF, 1, 0 );
/* Enter Normal Mode */
C1CTRL1bits.REQOP = 0;
while( C1CTRL1bits.OPMODE != 0 );
/* ECAN transmit/receive message control */
C1RXFUL1 = C1RXFUL2 = C1RXOVF1 = C1RXOVF2 = 0x0000;
C1TR01CONbits.TXEN0 = 1; /* ECAN1, Buffer 0 is a Transmit Buffer */
C1TR01CONbits.TXEN1 = 1; /* ECAN1, Buffer 1 is a Transmit Buffer */
C1TR23CONbits.TXEN2 = 1;
C1TR23CONbits.RTREN2 = 1 ; // Set TX Buffer0 as Auto response to Remote Transfer request - For exercise 5
C1TR01CONbits.TX0PRI = 0b11; /* Message Buffer 0 Priority Level */
C1TR01CONbits.TX1PRI = 0b11; /* Message Buffer 0 Priority Level */
C1TR23CONbits.TX2PRI = 0b11; /* Message Buffer 0 Priority Level */
/* Setup I/O pins */
// The PPS configuration varies from device to device. Refer the datasheet of the device being used and
// use the appropriate values for the RPINR/RPOR registers.
RPINR26bits.C1RXR = 108; //set CAN1 RX to RP108 (40)
RPOR12bits.RP109R = 14; //RPOR12bits.RP109R = 14; set CAN1TX to RP109 (39)
}
/******************************************************************************
* Function: void Ecan1WriteRxAcptFilter(int16_t n, int32_t identifier,
* uint16_t exide,uint16_t bufPnt,uint16_t maskSel)
*
* PreCondition: None
*
* Input: n-> Filter number [0-15]
* identifier-> Bit ordering is given below
* Filter Identifier (29-bits) :
* 0b000f ffff ffff ffff ffff ffff ffff ffff
* |____________|_____________________|
* SID10:0 EID17:0
*
* Filter Identifier (11-bits) :
* 0b0000 0000 0000 0000 0000 0fff ffff ffff
* |___________|
* SID10:
* exide -> "0" for standard identifier
* "1" for Extended identifier
* bufPnt -> Message buffer to store filtered message [0-15]
* maskSel -> Optinal Masking of identifier bits [0-3]
*
* Output: None
*
* Side Effects: None
*
* Overview: Configures Acceptance filter "n" for ECAN1.
*****************************************************************************/
void Ecan1WriteRxAcptFilter( int16_t n, int32_t identifier, uint16_t exide, uint16_t bufPnt, uint16_t maskSel )
{
uint32_t sid10_0 = 0;
uint32_t eid15_0 = 0;
uint32_t eid17_16 = 0;
uint16_t *sidRegAddr;
uint16_t *bufPntRegAddr;
uint16_t *maskSelRegAddr;
uint16_t *fltEnRegAddr;
C1CTRL1bits.WIN = 1;
// Obtain the Address of CiRXFnSID, CiBUFPNTn, CiFMSKSELn and CiFEN register for a given filter number "n"
sidRegAddr = ( uint16_t * ) ( &C1RXF0SID + (n << 1) );
bufPntRegAddr = ( uint16_t * ) ( &C1BUFPNT1 + (n >> 2) );
maskSelRegAddr = ( uint16_t * ) ( &C1FMSKSEL1 + (n >> 3) );
fltEnRegAddr = ( uint16_t * ) ( &C1FEN1 );
// Bit-filed manupulation to write to Filter identifier register
if( exide == 1 )
{ // Filter Extended Identifier
eid15_0 = ( identifier & 0xFFFF );
eid17_16 = ( identifier >> 16 ) & 0x3;
sid10_0 = ( identifier >> 18 ) & 0x7FF;
*sidRegAddr = ( ((sid10_0) << 5) + 0x8 ) + eid17_16; // Write to CiRXFnSID Register
*( sidRegAddr + 1 ) = eid15_0; // Write to CiRXFnEID Register
}
else
{ // Filter Standard Identifier
sid10_0 = ( identifier & 0x7FF );
*sidRegAddr = ( sid10_0 ) << 5; // Write to CiRXFnSID Register
*( sidRegAddr + 1 ) = 0; // Write to CiRXFnEID Register
}
*bufPntRegAddr = ( *bufPntRegAddr ) & ( 0xFFFF - (0xF << (4 * (n & 3))) ); // clear nibble
*bufPntRegAddr = ( (bufPnt << (4 * (n & 3))) | (*bufPntRegAddr) ); // Write to C1BUFPNTn Register
*maskSelRegAddr = ( *maskSelRegAddr ) & ( 0xFFFF - (0x3 << ((n & 7) * 2)) ); // clear 2 bits
*maskSelRegAddr = ( (maskSel << (2 * (n & 7))) | (*maskSelRegAddr) ); // Write to C1FMSKSELn Register
*fltEnRegAddr = ( (0x1 << n) | (*fltEnRegAddr) ); // Write to C1FEN1 Register
C1CTRL1bits.WIN = 0;
}
void Check_CAN_FIFO(void) {
if (C1FIFObits.FBP != C1FIFObits.FNRB) {
RXFUL_Var = C1FIFObits.FNRB;
FRAME_Buffer1.SID = (ecan1msgBuf[RXFUL_Var][0] >> 2) & 0x07ff;
if (FRAME_Buffer1.SID == EXT_VR1_ID) {
FRAME_Buffer1.DataWord0 = ecan1msgBuf[RXFUL_Var][3]; // Read ADC Value -- It at 1st word
FRAME_Buffer1.DATA_IN = 1;
Nop();
Nop();
}
RXFUL_Var = 0xfffe;
for (RXFUL_Loop = 0; RXFUL_Loop < C1FIFObits.FNRB; RXFUL_Loop++)
RXFUL_Var <<= 1;
C1RXFUL1 &= RXFUL_Var; // Clear RXFUL Flag ...
}
}
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